As the dimensions of field effect transistors (FETs) decrease, lithographic constraints are tending toward the gates of the FETs to be orientated in a single direction on a fixed pitch. When SRAM (static random access memory) cells are fabricated using these gate lithographic constraints it is becoming more difficult to fabricate storage node connections using the metal contact level. Accordingly, there exists a need in the art to mitigate the deficiencies and limitations described hereinabove.